ELECTRONIC INTERPOSER PROCESS DESIGN KIT (PDK)
Our Si electronic interposer consists of three front side Cu wiring levels and 10um x 100um through silicon vias (TSVs) connected to a single backside Cu redistribution layer. The front side has an option for Al termination as a custom offering.
Design rule check is supported in Cadence PVS, Synopsys ICV, and KLayout.
Current Version
The current PDK version that should be used for electronic interposer MPW runs is 0.6.
Component Libraries
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