NSF Dear Colleague Letter Instructions
See Dear Colleague Letter (DCL) NSF 21-015
Research on Integrated Photonics Utilizing AIM Photonics Capabilities
https://www.nsf.gov/publications/pub_summ.jsp?ods_key=nsf21015
October 15, 2020
The steps shown below will help interested parties understand what will be needed prior to submitting an NSF proposal in response to the DCL for an integrated silicon photonics project utilizing AIM Photonics capabilities.
1. Process Design Kit (PDK) Access
There are two PDKs available for AIM Photonics’ chip fabrication processes (Full-active Silicon Photonics Process, and Passive Silicon Photonics Process). More information about the PDKs can be found at http://www.aimphotonics.com/process-design-kit. These PDKs can be accessed from the AIM Photonics web site after the proper agreements are in place with AIM’s parent organization, The Research Foundation for the State University of New York (RF SUNY), as follows:
RF SUNY agreements needed:
a. To begin the engagement process with AIM Photonics, please fill out the form at http://www.aimphotonics.com/info-request
b. To be approved by AIM Photonics for PDK access, please visit the URL: http://www.aimphotonics.com/pdk-access-request
Notes on Design Intellectual Property (IP) Ownership and Protection:
Design IP that is not funded by AIM Photonics is not shared with AIM Photonics’ members or any other organization. Design IP that is funded by an NSF grant or other non-AIM Photonics sources is not considered to be the property of AIM Photonics. This IP remains the property of the design IP owner and is not shared with AIM Photonics members. AIM Photonics will need access to the design in order to prepare the Multi-Project-Wafer (MPW) and run it through our chip fab. The above agreements will bind AIM Photonics to protect the design IP and not share it with any other organization.
2. Multi-Project Wafer (MPW) Access
There are three (3) types of MPW fabrication runs (“runs”) planned which correspond to the two (2) PDK types (Base-Passive, Base Active). To reserve a rider slot on any of the MPW runs, you must request a quotation for your desired MPW run and submit a 20% deposit or an approved purchase order per the terms of the quotation. The balance due will be invoiced upon design submission and acceptance by AIM Photonics. Invoicing and payment terms for government entities will follow federal guidelines. To initiate a request for a quotation, please fill out the form at https://www.aimphotonics.com/info-request. The MPW schedules and more information about the MPW runs can be found at https://www.aimphotonics.com/mpw. Completed designs for any type of MPW run must be submitted to AIM Photonics on or before the design due date shown on these sites.
3. MPW design size and cost
The MPW runs are standardized and offered in fixed sizes as shown below. Note that member pricing is detailed here. For more information about pricing, please see the either the Base Active description or the Base Passive description
Full-active-Large — Offered in 50 mm2 sizes (6.19 mm x 8.69 mm) at $100,000 per chip set (n = 20)
Full-active-Medium — Offered in 25 mm2 sizes (6.19mm x 4.34mm) at $50,000 per chip set (n = 20)
Full-active-Small — Offered in 8 mm2 sizes (2.056 mm x 4.340 mm) at $25,000 per chip set (n = 20)
Base Passive-Large — Offered in 100 mm2 sizes (12.39 mm x 8.69 mm or 6.19 mm X 17.39 mm) at $100,000 per chip set ( n = 20)
Base Passive-Medium — Offered in 50 mm2 sizes (6.0 mm x 8.5 mm) at $30,000 per chip set (n = 20)
Base Passive-Small — Offered in 25 mm2 sizes (6.19mm x 4.34mm) at $20,000 per chip set (n = 20)
The sizes stated above are the standard AIM Photonics MPW sizes and cannot be changed at this time. However it is very possible for design teams to coordinate together and subdivide one of the standard size chips for their own purposes (e.g., for a teaching lab). The only requirement for subdividing is that the standard chip design submitted to AIM Photonics must be submitted by a single design team which handles all design issues, questions and individual design team interactions for the subdivided chip. i.e., all design support for the subdivided chip design must be handled by a single customer.
For proposals submitted to NSF and recommended for funding following merit review, the grantee’s cost of the Full-Active, or Passive chip may be reduced to 50% of the stated cost, based on available space on the MPW run. Availability will be confirmed two weeks prior to AIM Photonics’ final design submission due date.
4. Design Preparation
Once the PDK is obtained, a design team can prepare their design in their software tools of choice such that is fits within the provided design “frame.” All AIM Photonics PDKs are created to work with the Electronic/Photonic Design Automation (EPDA) software tools from six (6) different software vendors: Cadence Design Systems, Lumerical, Klayout, Luceda, Mentor Graphics, and Synopsys. AIM Photonics is currently not providing access to EPDA software for NSF projects. Thus each design team will need to acquire appropriate EPDA software for their design. All of the above listed EPDA companies have special low cost programs for academic institution access. Contact these companies directly (via their websites) for more information about their software. If EPDA company contact assistance is needed, please send an email to support@aimphotonics.com requesting assistance.
Probably the most critical task for each chip design is passing Design Rule Checking (DRC) prior to design submission to AIM Photonics. It is the design team’s responsibility to acquire access to the DRC rule deck from the PDK to run DRC checks on their design. The design must be DRC clean (no errors) prior to submission to AIM Photonics. The design team is responsible for fixing their design so it passes DRC before submission to AIM Photonics. There is a process to request a design rule waiver; sample Waiver Forms are located in the Design Guide. The associated PowerPoint presentation must be submitted along with the GDS-II submission to allow the Waiver Review Board time to assess your request and either accept or reject it.
5. Training
Designers will need to be able to perform the various steps of chip design including, but not limited to, design environment setup, detailed design layout, simulation, physical verification (DRC), and design extraction to GDS-II format.
6. Design Submission for MPW Fabrication
Final completed designs for a MPW run must be submitted on or before the design due dates as listed on the MPW schedules. All final designs must be DRC clean before submission.
In the event some of the above AIM Photonics website links are updated or changed, you can send an email to support@aimphotonics.com for questions.