See Dear Colleague Letter NSF 18-095 Dear Colleague Letter: Research on Integrated Photonics Utilizing AIM Photonics Capabilities July 20, 2018 (

The following steps will help interested parties understand what will be needed prior to submitting an NSF proposal in response to the DCL for an integrated silicon photonics project utilizing AIM Photonics capabilities.

1.       Process Design Kit (PDK) Access—For the intended design, there are three AIM PDKs available (Full-active Silicon Photonics Process, Passive Silicon Photonics Process, and Interposer Silicon Photonics Process). More information about the PDKs can be found at  All of these PDKs can be accessed from the MOSIS site after the proper agreements are in place with AIM Photonics and MOSIS as follows:

Design IP that is not funded by AIM Photonics is not shared with AIM members or any other organization. Design IP funded by an NSF grant or some other non-AIM source are not considered to be AIM Photonics projects and thus remain the property of the design IP owner and are not shared with AIM Photonics members. Obviously, MOSIS and the AIM foundry will need access to the design IP in order to prepare the MPW and fabricate it in the foundry. The above agreements will bind MOSIS and the foundry to protect the design IP and not share it with any other organization.

2.       Multi-Project Wafer (MPW) Access— There are 3 types of MPW fabrication runs (“runs”) planned which correspond to the 3 PDK types (Full-active, Passive, Interposer). The MPW schedules can be found on both the AIM Photonics and MOSIS websites as follows:   and . To reserve a rider slot on any of the MPW runs, you must request a quotation for your desired MPW run and pay a down payment of 20% per the terms of the quotation. The balance due will be invoiced upon design submission and acceptance by MOSIS. To initiate a quotation, please either fill out the form at or send an email to  Either of these methods will initiate the creation of an MPW quotation with payment terms.  More information about the MPW runs can be found at Completed designs for any type of MPW run must be submitted to MOSIS on or before the design due date shown on these sites.

3.       MPW design size and cost— The MPW runs are standardized and offered in fixed sizes as follows:

  • Full-active-Large —  Offered in 51 sq mm sizes (6.0 mm x 8.5 mm) at $100,000 per chip
  • Full-active- Small —  Offered in 8.1 sq mm sizes (1.93 mm x 4.2 mm) at $25,000 per chip
  • Passive —  Offered in 51 sq mm sizes (6.0 mm x 8.5 mm) at $30,000 per chip
  • Interposer — Offered in 156 sq mm sizes (12.0 mm x 13.0 mm) at $93,600 per chip

The sizes stated above are the standard AIM MPW sizes and cannot be changed at this time. However it is very possible for design teams to coordinate together and subdivide one of the standard size chips for their own purposes (e.g., for a teaching lab). The only requirement for subdividing is that the standard chip design submitted to MOSIS must be submitted by a single design team which handles all design issues, questions and individual design team interactions for the subdivided chip. i.e., all design support for the subdivided chip design must be handled by a single MOSIS customer.

For proposals submitted to NSF and recommended for funding following merit review, the grantee’s cost of the Full-Active, Passive, or Interposer chip may be reduced to 50% of the stated cost, based on co-funding to be provided by DoD.

4.       Design Preparation— Once the PDK is obtained, a design team can prepare their design in their software tools of choice such that is fits within the provided design “frame”. All AIM PDKs are created to work with the Electronic/Photonic Design Automation (EPDA) software tools from 5 software companies: Cadence Design Systems, Lumerical, Mentor Graphics, PhoeniX Software, and Synopsys RSoft. AIM is currently not providing access to EPDA software for NIST projects. Thus each design team will need to acquire appropriate EPDA software for their design. All of the above listed EPDA companies have special low cost programs for academic institution access. Contact these companies directly (via their websites) for more information about their software. If EPDA company contact assistance is needed, please send an email to requesting assistance. Probably the most critical task for each chip design is passing Design Rule Checking (DRC) prior to design submission to MOSIS. It is the design team’s responsibility to acquire access to the Mentor Graphics Calibre software and use the DRC rule deck from the PDK to run Calibre DRC checks on their design. The design must be DRC clean (no errors) prior to submission to MOSIS. The design team is responsible for fixing their design so it passes DRC before submission to MOSIS. There is a design rule waiver process to ask for a waiver in your design. Fill out the Waiver Form located on the MOSIS PDK download site. The form must be submitted to as soon as possible to allow the Waiver Review Board time to assess your request and either accept or reject it.

5.       Training— Chip designers will need to be able to perform the various steps of chip design including, but not limited to, design environment setup, detailed design layout, simulation, physical verification (DRC), and design extraction to GDS-II format.

  • AIM Academy will eventually have courses available for practical chip design training, which will be posted to their website when available (
  • There will be a PDK/MPW Overview Training offered on a regular basis starting Q2 2017, which will be announced on the AIM website  This PDK/MPW Overview will provide information on topics like PDK contents and what you do with it, guidance on how to get started with a design, supported EPDA methodologies, requirements for submitted designs, and other “good to know” information to enable new users of the AIM PDK/MPW to be successful.
  • EPDA Companies also provide extensive training for their software tools and methodologies. Many of these training opportunities will be coordinated and announced through the AIM website in 2017. Additionally, design teams are encouraged to directly contact the EPDA companies to inquire about training opportunities.

6.       Design Submission for MPW Fabrication— Preliminary designs are required to be submitted to MOSIS 30 days prior to the final due date. This allows MOSIS to begin their setup for accepting your final design on the due date. Final completed designs for any MPW run must be submitted to MOSIS on or before the design due dates as listed on the schedules mentioned above.  All final designs must be DRC clean before submission to MOSIS. After submission, MOSIS will also run DRCs. The steps for design submission are listed here: Note that the only “approvals” MOSIS does to accept a design are 1) verifying with AIM Photonics that the design team is authorized for MPW submission, and 2) verifying that the design is DRC clean. The design team is required to do these exact same DRC checks prior to design submission.

In the event some of the above AIM Photonics website links are updated or changed, you can send an email to for questions.